In the integrated circuit industry, it has long been the practice to locate both data processing circuitry and memory storage circuitry on the same integrated circuit (IC) or “chip.” This is especially the case for complex ICs such as microprocessors. In fact, there are typically a number of different memory arrays on a single microprocessor chip. The memory arrays can come in different forms and sizes and may perform a variety of general or dedicated functions. For example, one memory array may be an instruction cache and another may be a data cache. At various times in the life of any IC, it becomes necessary or desirable to test these memory arrays for structural defects. Conventionally, memory array testing can be performed by providing test stimulus and observing test response externally, internally, or a combination of the two. As the number and complexity of the memory arrays have increased, the dependence on external testing alone has decreased. External testing requires expensive tester resources such as automatic test equipment (ATE). Also, external testing alone is performed at a slower speed than can be achieved through internal testing. Internal testing can be performed at the rated speed of the chip being tested. At-speed testing takes less time and gives better defect detection capability. Memory testing by way of internal or on-chip circuitry is known as memory built-in self-test (memory BIST or MBIST) or array built-in self-test (array BIST or ABIST). Generally, the main component of the circuitry, called an MBIST engine, performs one or more test algorithms on one or more of the various memory arrays. For memory testing, one class of algorithms is known as the March algorithms for the methodical way the test sequence advances from one memory location to another. There are a number of March algorithms popular in the industry because the various test algorithms target different defect mechanisms or faults. It may be that more than one test algorithm is desired or required to identify the various types of faults. For example, one March algorithm, known as the moving inversions (MOVI) test, sequentially writes and reads through the memory array in such a way that all single stuck-at faults, address faults, transition faults, and coupling faults in the memory array may be detected. Generally, the on-chip test circuitry is organized in either a central or a distributed configuration. In the central configuration, there is one MBIST engine which controls the testing of all of the various memory arrays. In the distributed configuration, there is a dedicated MBIST engine that controls the testing of a specific memory array. Each of the dedicated MBIST engines is located in close proximity to its associated memory array. By general comparison, the former has less circuitry that is more complicated and the latter has more total circuitry that is less complicated. Further, the former has more wire routing in terms of length than the latter.
Taken together, the memory space of the various memory arrays in the IC can be logically viewed as the complete address space of the IC. The individual memory arrays are then viewed as a logical partition of this unified address space. The individual memory arrays can be identified by their address locations in the unified address space. One example of such organization, called the Address Space Identifier (ASI) architecture, is provided by the Scalable Processor ARChitecture (SPARC) microprocessor specification. The SPARC specification is an open specification created by the SPARC Architectural Committee of SPARC International. One can implement a microprocessor chip that is compliant with the SPARC specification by securing a license from SPARC International. The SPARC specification is well known and will serve as the basis of the discussion that follows. However, this is not to be interpreted as meaning that the following discussion is strictly limited to the SPARC specification.
Turning first to FIG. 1, a block diagram of relevant portions of an IC 10 is shown. The IC 10 includes a memory control unit (MCU) 12, core logic 14, ASI bus interface logic 16, and one or more memory arrays 18. The ASI bus interface logic 16 and the memory arrays 18 are connected by the ASI bus as shown. One of ordinary skill in the art will recognize that a conventional IC will likely include other blocks that are not shown here in the interest of clarity. The core logic 14 may include a wide assortment of logic for data processing. The core logic 14 may not necessarily be a single entity as shown. The block designated as memory arrays 18 may include any number of memory arrays. The various memory arrays will likely come in different forms and sizes and will likely be located in different regions of the IC. All of the various memory arrays are accessible via an ASI bus. The protocol of the ASI bus is controlled by the ASI bus interface logic 16. The ASI bus may be connected to the ASI bus interface logic 16 in any number of arrangements. The SPARC specification does not dictate the arrangement to be used. Two common arrangements are a loop and a star topology. In the loop topology, a first memory array is connected to the ASI bus interface logic 16 and to a second memory array. The second memory array is in turn connected to a third memory array which is in turn connected to the next memory array. This pattern is continued until the last memory array is connected back to the ASI bus interface logic 16. The memory arrays are said to form a loop or chain. In the star topology, each of the memory arrays is connected directly to the ASI bus interface logic 16 in a radiating pattern that is said to resemble a star. Other arrangements and combinations of arrangements exist. The actual arrangement is not critical so long as, whatever the arrangement, it is known by the ASI bus interface logic 16 so that any latency of accessing a specific memory array can be accounted for. Of course, for the IC designer, the actual arrangement will have implications on the routing area required for the physical implementation of the network of memory arrays 18.
Each of the various memory arrays 18 will include a plurality of memory locations (not shown). The number of memory locations will depend on the circumstances such as the function of the specific memory array. According to the current SPARC specification each of the memory locations is identified by an address consisting of two elements. The first element is a unique ASI for each memory array which distinguishes one memory array from another. For example, if the memory arrays 18 include an instruction cache and a data cache, then each will have a different ASI. The second element is an address which identifies an offset into its associated address space which corresponds to a particular memory location. Taken together, the two elements guarantee that each memory location on the IC has a unique address. The SPARC ASI specification also currently stipulates a data field, a read-strobe, and a write-strobe. Taken together these elements are collectively referred to as the ASI bus protocol of a SPARC microprocessor. The ASI bus standardizes the access of all of the memory arrays without necessitating knowledge of their physical structure.